Content addressable memory (CAM) arrays are commonly used in cache systems, and other address translation systems, of high speed computing systems. They are also useful in high-speed network routers, and many other applications known in the art of computing.
The CAM arrays are typically comprised of a plurality of rows, each row having multiple CAM blocks and each CAM block has plurality of CAM cells. The CAM arrays are characterized by circuitry capable of generating a “local match” output for each CAM block in a row and a “global match” output for each row of CAM blocks in the CAM array thereby indicating whether any location of the array contains a data pattern that matches a query input and the identity of that location. Each CAM cell of a CAM array typically has the ability to store a unit of data, and the ability to compare that unit of data with a unit of a query input. Each CAM block has the ability to generate the local match output. A compare result indication of each CAM block, which is a local match (LMAT) signal, in a row is combined to produce a global match (GMAT) signal for the row to indicate whether the row of CAM cells contains a stored word matching a query input. The GMAT signals from each row in the CAM array together constitute global match output signals of the array; these signals may be encoded to generate the address of matched locations or used to select data from rows of additional memory.
Each CAM cell in each column of a CAM array is typically connected to a common read/write bit line and a search bit line. The common read/write bit line is used to write the data to a pair of memory cells, which can be part of a ternary CAM (TCAM) cell or a single memory cell, such as a binary CAM. Each memory cell is accessed using a word line which is decoded using an input address. The common read/wire bit line is also used for reading the data from a memory cell. The differential developed across the read/write bit lines are sensed using a sense amplifier during a read cycle.
Further, each CAM cell in each column in the CAM arrays is typically connected to a common query data line, also referred to as a common search data line. The common search data line enables simultaneous data searching in each CAM cell in a column from a query input. The common search data line can also be used as a write data line, when the CAM array is based on a PMOS compare circuit.
The unit of data that is stored in a CAM array cell is often binary, having two possible states: logic one, and logic zero. The CAM blocks of these arrays produce a local match compare result if the query input is equal to the data stored in the CAM cells in the CAM blocks, and a mismatch result if otherwise. Whereas, TCAM cells can store three states: logic one, logic zero, and don't care. TCAM blocks of these TCAM arrays produce a local match compare result if either the query input is equal to the data stored in the CAM cells in the TCAM blocks, the query input contains a don't care state, or the data stored is a don't care data. The TCAM arrays produce a mismatch result otherwise. The TCAM arrays are particularly useful in address translation systems that allow variably sized allocation units.
Typically, in a CAM array, the common read/write bit lines are precharged after each write or read cycle using precharge devices. Generally, for larger memories, the precharge devices are located on either end of the write bit lines to decrease precharge time. In general, the precharge time affects the cycle time of a CAM. In a read cycle, the read/write bit lines are not allowed to discharge to ground and can be precharged back after a required differential is built up. Whereas, in a write cycle, the read/write bit lines discharge all the way to ground and hence the time required to precharge the read/write bit lines after a write cycle can be considerably higher than the time required to precharge the read/write bit lines after a read cycle and therefore can affect the cycle time.
One conventional technique uses significantly large precharge devices to reduce the time required to precharge during a write cycle. Another conventional technique partitions the CAM array into smaller sections to reduce the time required to precharge after a write operation. However, these techniques generally result in requiring a larger silicon area and can be very cumbersome to implement.